Fan-out wafer level packaging (“FOWLP”) processes often entail the formation of redistribution layers over the surface of a die package, which includes a molded package body in which one or more semiconductor die carrying integrated circuits (“ICs”) are embedded. The redistribution layers provide electrical interconnection between contact pads located on the IC die and a contact array, such as a ball grid array, formed over a surface of the completed die package. In this manner, the redistribution layers allow the contact pads to have a relatively tight pad-to-pad spacing or pitch, while still providing a comparably large surface area over which the the contact array can be distributed or fanned-out. To produce the redistribution layers, one or more layers of dielectric or passivation material are initially deposited over the IC die and cover the contact pads. In one conventional approach, a separate via is etched through the dielectric layer to expose a portion of each contact pad, metal plugs or other conductors are then formed in each via to provide ohmic contact with the contact pad, and then a circuit or interconnect line is formed in contact with each conductor. More recently, an improved approach has been introduced wherein a single elongated via referred to as a “trench via” is formed to simultaneously expose multiple contact pads through the overlying dielectric, and interconnect lines are subsequently formed to extend into the trench via and directly contact the contact pads located therein. Such an approach enables fine pitch interconnect structures to be produced in the redistribution layers in an efficient and reliable manner.
For simplicity and clarity of illustration, the drawing figures illustrate the general manner of construction and may omit depiction, descriptions, and details of well-known features and techniques to avoid unnecessarily obscuring the exemplary and non-limiting embodiments of the invention described in the subsequent Detailed Description. It should further be understood that features or elements appearing in the accompanying figures are not necessarily drawn to scale unless otherwise stated. For example, the dimensions of certain elements or regions in the figures may be exaggerated relative to other elements or regions to improve understanding of embodiments of the invention.